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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 114 db, 192 khz 6 -channel d/a converter features ? advanced multi-bit delta sigma architecture ? 24-bit conversion ? up to 192 khz sample rates ? 114 db dynamic range ? -100 db thd+n ? direct stream digital mode ? on-chip 50 khz filter ? matched pcm and dsd analog output levels ? selectable digital filters ? volume control with 1-db step size and soft ramp ? low clock jitter sensitivity ? +5 v analog supply, +2.5 v digital supply ? separate 1.8 to 5 v logic supplies for the control & serial ports description the cs4362a is a complete 6-channel digital-to-analog system. this d/a system includes digital de-emphasis, one-db step size volume control, atapi channel mix- ing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma mod- ulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. follow- ing this stage is a multi- element switched capacitor stage and low-pass filter with differential analog outputs. the cs4362a also has a proprietary dsd processor which allows for 50 khz on-ch ip filtering without an in- termediate decimation stage. the cs4362a accepts pcm data at sample rates from 4 khz to 216 khz, dsd audio data, and delivers excel- lent sound quality. these features are ideal for multi- channel audio systems including sacd players, a/v re- ceivers, digital tv?s, mixing consoles, effects processors, sound cards and automotive audio systems. ordering information see page 41. control port supply = 1.8 v to 5 v register/hardware configuration internal voltage reference reset serial interface level translator level translator digital supply = 2.5 v hardware mode or i 2 c/spi software mode control data analog supply = 5 v six channels of differential outputs pcm serial audio input volume controls digital filters switch-cap dac and analog filters multi-bit ? modulators dsd audio input dsd processor -50 khz filter external mute control mute signals serial audio port supply = 1.8 v to 5 v 6 6 6 6 apr '05 ds617pp1 cs4362a
2 ds617pp1 cs4362a table of contents 1. pin description............................................................................................................. ........ 6 2. characteristics and specif ications........ ................ ............. ............. ............. ........... 8 3. applications ................................................................................................................ ....... 20 3.1 master clock............................................................................................................... ...... 20 3.2 mode select................................................................................................................ ...... 20 3.3 digital interface formats .................................................................................................. 22 3.4 oversampling modes........................................................................................................ 2 3 3.5 interpolation filter ....................................................................................................... ...... 23 3.6 de-emphasis ................................................................................................................ .... 23 3.7 atapi specification ........................................................................................................ .. 24 3.8 direct stream digital (dsd) mode.................................................................................... 25 3.9 grounding and power supply arrangements ................................................................... 25 3.9.1 capacitor placement............................................................................................ 25 3.10 analog output and filtering ............................................................................................ 25 3.11 mute control .............................................................................................................. ..... 26 3.12 recommended power-up sequence ............. ................................................................ 27 3.12.1 hardware mode ................................................................................................. 27 3.12.2 software mode................................................................................................... 27 3.13 recommended proc edure for switching operational modes......................................... 27 3.14 control port interface ........................... ......................................................................... .28 3.14.1 map auto increment.......................... ................................................................ 28 3.14.2 i 2 c mode............................................................................................................ 28 3.14.2.1 i 2 c write ............................................................................................ 28 3.14.2.2 i 2 c read ............................................................................................ 29 3.14.3 spi? mode........................................................................................................ 30 3.14.3.1 spi write............................................................................................ 30 3.15 memory address pointer (map) ..... .......................................................................... 30 4. register quick reference ............................................................................................ 31 5. register description ...................................................................................................... 32 5.1 mode control 1 (address 01h) .......................................................................................... 32 5.1.1 control port enable (cpen) ................ ................................................................ 32 5.1.2 freeze controls (freeze)..................................................................................... 32 5.1.3 master clock divide enable (mclkdiv) ............................................................ 32 5.1.4 dac pair disable (dacx_dis) ............................................................................ 32 5.1.5 power down (pdn).............................................................................................. 33 5.2 mode control 2 (address 02h) ......................................................................................... 33 5.2.1 digital interface format (dif) ................................................................................ 33 5.2.2 mode control 3 (address 03h) ............................................................................ 34 5.2.3 soft ramp and zero cross control (szc) ................................................... 34 5.2.4 single volume control (snglvol) .......................................................................... 34 5.2.5 soft volume ramp-up af ter error (rmp_up) ..................................................... 35 5.2.6 mutec polarity (mutec+/-)............................................................................... 35 5.2.7 auto-mute (amute) ........................................................................................... 35 5.2.8 mute pin control (mutec1, mutec0) . .............................................................. 35 5.3 filter control (address 04h) ............................................................................................. 3 6 5.3.1 interpolation filter se lect (filt_sel).................................................................. 36 5.3.2 de-emphasis control (dem) ............................................................................... 36 5.3.3 soft ramp-down before filter mode change (rmp_dn) ................................... 36 5.4 invert control (address 05h) ............................................................................................ 37 5.4.1 invert signal polarity (inv_xx)........ ...................................................................... 37 5.5 mixing control pair 1 (channels a1 & b1)(address 06h) mixing control pair 2 (channels a2 & b2)(address 09h)
ds617pp1 3 cs4362a mixing control pair 3 (channels a3 & b3)( address 0ch) ............................................. 37 5.5.1 channel a volume = channel b volume (a=b)................................................... 37 5.5.2 atapi channel mixing and muting (atapi) ........................................................ 37 5.5.3 functional mode (fm).......................................................................................... 38 5.6 volume control (addresses 07h, 08h, 0ah, 0bh, 0dh, 0eh) .......................................... 39 5.6.1 mute (mute) ....................................................................................................... 39 5.6.2 volume control (xx_vol) .................................................................................... 39 5.7 chip revision (address 12h) ........................................................................................... 40 5.7.1 part number id (part) [read only] ...................................................................... 40 6. parameter definitions.................................................................................................... 41 7. references.................................................................................................................. ........ 41 8. ordering information .................................................................................................... 41 9. package dimensions ........................................................................................................ 42 10. appendix ......... ................. ................ ................ ................ ................ ............. ........... ........... 43
4 ds617pp1 cs4362a list of figures figure 1. serial audio interface timing........................................................................................ ............. 14 figure 2. direct stream digital - serial audio input timing.................................................................... ... 15 figure 3. control port timing - i 2 c format ............................................................................................... 16 figure 4. control port timing - spi format......... ............................................................................ .......... 17 figure 5. typical connection dia gram, software mode....... ..................................................................... 18 figure 6. typical connection diagr am, hardware mode .......................................................................... 1 9 figure 7. format 0 - left-justified up to 24-bit data .......................................................................... ....... 22 figure 8. format 1 - i 2 s up to 24-bit data................................................................................................. 22 figure 9. format 2 - right-justified 16-bit data ............................................................................... ......... 22 figure 10. format 3 - right-justified 24-bit da ta .............................................................................. ........ 22 figure 11. format 4 - right-justified 20-bit da ta .............................................................................. ........ 23 figure 12. format 5 - right-justified 18-bit da ta .............................................................................. ........ 23 figure 13. de-emphasis curve................................................................................................... .............. 24 figure 14. atapi block diagram (x = channel pair 1, 2, or 3) .................................................................. 24 figure 15. full-scale output ................................................................................................... .................. 26 figure 16. recommended output filter........................................................................................... ......... 26 figure 17. control port timing, i 2 c mode................................................................................................. 29 figure 18. control port timing, spi mode ....................................................................................... ......... 30 figure 19. single-speed (fast) stopband rejection.............................................................................. .... 43 figure 20. single-speed (fast) transition band .. ............................................................................... ....... 43 figure 21. single-speed (fast) transition band (d etail) ........................................................................ .... 43 figure 22. single-speed (fast) passband ripple ................................................................................. ..... 43 figure 23. single-speed (slow) stopband rejection .............................................................................. .. 43 figure 24. single-speed (slow) transition band................................................................................. ...... 43 figure 25. single-speed (slow) tr ansition band (detail)........................................................................ ... 44 figure 26. single-speed (slow) passband ripple................................................................................. .... 44 figure 27. double-speed (fast) stopband rejection .............................................................................. .. 44 figure 28. double-speed (fast) transition band..... ............................................................................ ...... 44 figure 29. double-speed (fast) tr ansition band (detail)........................................................................ ... 44 figure 30. double-speed (fast) passband ripple................................................................................. .... 44 figure 31. double-speed (slow) st opband rejection .............................................................................. . 45 figure 32. double-speed (slow) tr ansition band ................................................................................. .... 45 figure 33. double-speed (slow) tr ansition band (detail) ........................................................................ . 45 figure 34. double-speed (slow) passband ripple ................................................................................. .. 45 figure 35. quad-speed (fast) st opband rejection ................................................................................ ... 45 figure 36. quad-speed (fast) transition band ....... ............................................................................ ...... 45 figure 37. quad-speed (fast) tr ansition band (detail) .......................................................................... ... 46 figure 38. quad-speed (fast) passband ripple ........ ........................................................................... .... 46 figure 39. quad-speed (slow) st opband rejection................................................................................ .. 46 figure 40. quad-speed (slow) transition band.. ................................................................................. ..... 46 figure 41. quad-speed (slow) tran sition band (detail).......................................................................... .. 46 figure 42. quad-speed (slow) passband ripple....... ............................................................................ ... 46
ds617pp1 5 cs4362a list of tables table 1. common clock frequencies........................................................................................... 20 table 2. digital interface forma t, stand-alone mode options...................................................... 21 table 3. mode selection, stand-alone mode options .................................................................. 21 table 4. direct stream digital (dsd), stand-alone mode options ............................................... 21 table 5. digital interface formats - pcm mode.. .......................................................................... 33 table 6. digital interface form ats - dsd mode ............................................................................ 33 table 7. atapi decode .......................................................................................................... ...... 38 table 8. example digital volume settings .......... .......................................................................... 39 table 9. revision history ..................................................................................................... ........ 47
6 ds617pp1 cs4362a 1. pin description pin name # pin description vd 4 digital power ( input ) - positive power supply for the digi tal section. refer to the rec- ommended operating conditions for appropriate voltages. gnd 5,31 ground ( input ) - ground reference. should be connected to analog ground. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. table 5 illustrates several sta ndard audio sample rates and the required master clock frequencies. lrck 7 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sdin1 sdin2 sdin3 8 11 13 serial data input ( input ) - input for two?s complement serial audio data. sclk 9 serial clock ( input ) - serial clocks for t he serial audio interface. tst 10,12 14,44 45 test - these pins need to be tied to analog ground. rst 19 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. va 32 analog power ( input ) - positive power supply for the analog section. refer to the recommended operating conditions for appropriate voltages. vls 43 serial audio interface power ( input ) - determines the required signal level for the serial audio interface. refer to the recommended operating conditions for appropri- ate voltages. vlc 18 control port power ( input ) - determines the required signal level for the control port and hardware mode configuration pins. refer to the recommended operating condi- tions for appropriate voltages. sdin3 gnd aoutb2- aouta3+ aoutb3- aoutb2+ va aouta3- aoutb3+ mutec2 mutec3 6 2 4 8 10 1 3 5 7 9 11 1 2 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mclk dsdb1 vd sdin1 tst dsda2 dsda1 gnd sclk sdin2 tst lrck(dsd_en) m3(dsd_sclk) dsdb3 dsda3 tst cs4362a tst vls tst m2(scl/cclk) m1(sda/cdin) vlc rst filt+ vq mutec6 mutec5 mutec4 m0(ad0/cs) aouta2+ aouta2- aoutb1+ aoutb1- aouta1- aouta1+ dsdb2 mutec1
ds617pp1 7 cs4362a vq 21 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vq must be capacitively coupled to analog gr ound, as shown in the typical connection diagram. the nominal voltage level is specified in the analog characteristics and specifications section. vq presents an appreciable source impedance and any cur- rent drawn from this pin will alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc cur- rent is less then the maximum specified in the analog characteri stics and specifica- tions section. filt+ 20 positive voltage reference ( output ) - positive reference volt age for the internal sampling circuits. requires the capacitive decoupling to analog ground as shown in the typical connection diagram. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- 39,40 38,37 35,36 34,33 29,30 28,27 differential analog output ( output ) - the full scale differential analog output level is specified in the analog charac teristics specification table. mutec1 mutec2 mutec3 mutec4 mutec5 mutec6 41 26 25 24 23 22 mute control ( output ) - the mute control pins go high during power-up initialization, reset, muting, power-do wn or if the master clock to left/right clock frequency ratio is incorrect. these pins are intended to be used as a control for external mute circuits on the line outputs to prevent the clicks and pops that can occur in any single supply sys- tem. use of mute control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. hardware mode definitions m0m1 m2 m3 17 16 15 42 mode selection ( input ) - determines the operational mode of the device as detailed in tables 6 and 7. software mode definitions scl/cclk 15 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i 2 c mode as shown in the typical connection diagram. sda/cdin 16 serial control port data ( input/output ) - sda is a data i/o line in i 2 c mode and is open drain, requiring an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram; cdin is the input data line for the control port interface in spi mode. ad0/cs 17 address bit 0 (i 2 c) / control port chip select (spi) ( input ) - ad0 is a chip address pin in i 2 c mode; cs is the chip select signal for spi mode. dsd definitions dsda1 dsdb1 dsda2 dsdb2 dsda3 dsdb3 3 2 1 48 47 46 direct stream digital input ( input) - input for direct stream digital serial audio data. dsd_sclk 42 dsd serial clock (input) - serial clock for the direct stream digital serial audio interface. dsd_en 7 dsd enable (input) - when held at logic ?1? the device will enter dsd mode (stand-alone mode only). pin name # pin description
8 ds617pp1 cs4362a 2. characteristics and specifications all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specifications are deri ved from measurements taken at nominal supply voltage and t a = 25 c. specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyo nd these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.25 v v v v specified temperature range -cqz -eqz t a -10 -40 - - +70 +105 c c parameters symbol min max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 3.2 6.0 6.0 v v v v input current any pin except supplies i in -10ma digital input voltage serial data port interface control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t op -55 125 c storage temperature t stg -65 150 c
ds617pp1 9 cs4362a dac analog characteristics full-scale output sine wave, 997 hz (note 1) ; fs = 48/96/192 khz; test load r l = 3 k ? , c l = 100 pf ; measure- ment bandwidth 10 hz to 20 khz, unless otherwise specified. notes: 1. one-half lsb of triangular pdf dither is added to data. 2. performance limited by 16-bit quantization noise. parameters symbol min typ max unit CS4362A-CQZ dynamic performance - all pcm modes and dsd specified temperature range t a -10 - 70 c dynamic range 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 108 105 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - -45 - - - db db db db db db idle channel noise / signa l-to-noise ratio - 114 - db cs4362a-eqz dynamic performance - all pcm modes and dsd specified temperature range t a -40 - 105 c dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 105 102 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -91 - -42 - - - db db db db db db idle channel noise / signa l-to-noise ratio - 114 - db
10 ds617pp1 cs4362a dac analog characteristics - all modes (continued) power and therma l characteristics notes: 3. v fs is tested under load r l and includes attenuation due to z out 4. current consumption increases with increasing fs within a given speed mode and is signal dependant. max values are based on highest fs and highest mclk. 5. i lc measured with no external loading on the sda pin. 6. power down mode is defined as rst pin = low with all clock and data lines held static. 7. valid with the recommended capacitor values on filt+ and vq as shown in figures 5 and 6. parameters symbol min typ max units interchannel isolation (1 khz) - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output full scale differential- pcm, dsd processor output voltage direct dsd mode v fs 132%?v a 94%?v a 134%?v a 96%?v a 136%?v a 98%?v a vpp vpp output impedance (note 3) z out -130 - ? max dc current draw from an aout pin i outmax -1.0 -ma min ac-load resistance r l -3 -k ? max load capacitance c l -100 -pf quiescent voltage v q - 50% v a -vdc max current draw from v q i qmax -10 - a parameters symbol min typ max units power supplies power supply current normal operation, va= 5 v (note 4) vd= 2.5 v (note 5) interface current, vlc=5 v vls=5 v (note 6) power-down state (all supplies) i a i d i lc i ls i pd - - - - - 56 20 2 84 200 61 26 - - - ma ma a a a power dissipation (note 4) va = 5 v, vd = 2.5 v normal operation (note 6) power-down - - 332 1 372 - mw mw package thermal resistance ja jc - - 48 15 - - c/watt c/watt power supply rejection ratio (note 7) (1 khz) (60 hz) psrr - - 60 40 - - db db
ds617pp1 11 cs4362a combined interpolation & on-c hip analog filter response the filter characteristics have been normalized to the samp le rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs. (see note 12.) notes: 8. slow roll-off interpolation filter is only available in software mode. 9. response is clock dependent and will scale with fs. 10. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement ba ndwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single-speed mode; only 44.1 khz de-emphasis is available in hard- ware mode. 12. amplitude vs. frequency pl ots of this data are available starting on page 43. parameter fast roll-off unit min typ max combined digital and on-chip analog filt er response - single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 10) 102 - - db group delay - 10.4/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 80 - - db group delay - 6.15/fs - s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .635 - - fs stopband attenuation (note 10) 90 - - db group delay - 7.1/fs - s
12 ds617pp1 cs4362a combined interpolat ion & on-chip analog filter response (contined) dsd combined digital & on- chip analog filter response parameter slow roll-off (note 8) unit min typ max single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 64 - - db group delay - 7.8/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.36 0.21 0.14 db db db double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .792 - - fs stopband attenuation (note 10) 70 - - db group delay - 5.4/fs - s quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .868 - - fs stopband attenuation (note 10) 75 - - db group delay - 6.6/fs - s parameter min typ max unit dsd processor mode passband (note 9) to -3 db corner 0 - 50 khz frequency response 10 hz to 20 khz -0.05 - +0.05 db roll-off 27 - - db/oct
ds617pp1 13 cs4362a digital characteristics 13. any pin except supplies. transien t currents of up to 100 ma on the input pins will not cause scr latch- up parameters symbol min typ max units input leakage current (note 13) i in --10 a input capacitance - 8 - pf high-level input voltage serial i/o control i/o v ih v ih 70% 70% - - - - v ls v lc low-level input voltage serial i/o control i/o v il v il - - - - 30% 30% v ls v lc high-level output voltage (i oh = -1.2 ma) control i/o v oh 80% - - v lc low-level output voltage (i ol = 1.2 ma) control i/o v ol --20%v lc maximum mutec drive current i max -3-ma mutec high-level output voltage v oh -va-v mutec low-level output voltage v ol -0-v
14 ds617pp1 cs4362a switching characteristics - pcm (inputs: logic 0 = gnd, logic 1 = vls, c l = 30 pf) notes: 14. after powering up, rst should be held low until after the power supplies and clocks are settled. 15. see table 1 on page 20 for suggested mclk frequencies. parameters symbol min max units rst pin low pulse width (note 14) 1 - ms mclk frequency 1.024 55.2 mhz mclk duty cycle (note 15) 45 55 % input sample rate - lrck single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 54 108 216 khz khz khz lrck duty cycle 45 55 % sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns lrck edge to sclk rising edge t lcks 5-ns sdin setup time befo re sclk rising edge t ds 3-ns sdin hold time after sclk rising edge t dh 5-ns sdinx t ds sclk lrck msb t dh t sckh t sckl t lcks msb-1 figure 1. serial audio interface timing
ds617pp1 15 cs4362a switching charact eristics - dsd (logic 0 = agnd = dgnd; logic 1 = vls; c l =20pf) parameter symbol min typ max unit mclk duty cycle 40 - 60 % dsd_sclk pulse width low t sclkl 160 - - ns dsd_sclk pulse width high t sclkh 160 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns sclkh t sclkl t dsdxx dsd_sclk sdlrs t sdh t figure 2. direct stream digital - serial audio input timing
16 ds617pp1 cs4362a switching characteristics - control port - i 2 c format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 16. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 3. control port timing - i 2 c format
ds617pp1 17 cs4362a switching characteristics - control port - spi ? format (inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 17. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 18. data must be held for sufficient time to bridge the transition time of cclk. 19. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 17) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 18) t dh 15 - ns rise time of cclk and cdin (note 19) t r2 -100ns fall time of cclk and cdin (note 19) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 4. control port timing - spi format
18 ds617pp1 cs4362a vls mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ cmout 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 13 analog conditioning and muting aouta1- aoutb1+ 38 37 analog conditioning and muting aoutb1- aouta2+ 35 36 analog conditioning and muting aouta2- aoutb2+ 34 33 analog conditioning and muting aoutb2- aouta3+ 29 30 analog conditioning and muting aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- mutec1 41 26 mute drive mutec2 11 micro- controller vlc 0.1 f +1.8 v to +5 v 18 2 48 dsdb2 3 42 dsd_sclk dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 16 15 scl/cclk sda/cdin ado/cs rst 19 17 2 k ? 2 k ? note*: necessary for i 2 c control port operation note* mutec3 25 24 mutec4 mutec5 23 22 mutec6 cs4362a 31 gnd gnd 5 tst 10, 12, 14, 44, 45 dsd audio source 220 ? 470 ? 470 ? digital audio source pcm figure 5. typical connection diagram, software mode
ds617pp1 19 cs4362a vls cs4362a mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ cmout 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 13 aouta1- aoutb1+ 38 37 aoutb1- aouta2+ 35 36 aouta2- aoutb2+ 34 33 aoutb2- aouta3+ 29 30 aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- 11 vlc 0.1 f +1.8 v to +5 v 18 dsd 2 48 dsdb2 3 42 m3(dsd_sclk) dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 m2 m1 m0 rst 47 k ? vls note dsd note dsd note dsd : for dsd operation: remain static high. 2) m3 pcm stand-alone configuration pin becomes dsd_sclk 22 mutec6 analog conditioning and muting 23 mutec5 analog conditioning and muting 24 mutec4 analog conditioning and muting 25 mutec3 analog conditioning and muting 26 mutec2 analog conditioning and muting 41 mutec1 stand-alone mode configuration 1) lrck must be tied to vls and 31 gnd gnd 5 tst 10, 12, 14, 44, 45 digital audio source pcm audio source 220 ? 470 ? 470 ? 16 15 19 17 47 k ? optional figure 6. typical connection diagram, hardware mode
20 ds617pp1 cs4362a 3. applications the cs4362a serially accepts twos complement formatted pcm data at standard audio sample rates including 48, 44.1 and 32 khz in ssm, 96, 88.2 and 64 khz in dsm, and 192, 176.4 and 128 khz in qsm. audio data is input via the serial data input pins (sdinx). the left/right clo ck (lrck) determines which channel is currently being input on sdinx, and the serial clock (sclk) clo cks audio data into the input data buffer. the cs4362a can be configured in hardware mode by the m0, m1, m2 , m3 and dsd_en pins and in software mode through i 2 c or spi. 3.1 master clock mclk/lrck must be an integer ratio as shown in tabl e 1. the lrck frequency is equal to fs, the frequen- cy at which words for each channel are input to the de vice. the mclk-to-lrck frequency ratio is detected automatically during the initialization sequence by count ing the number of mclk transitions during a single lrck period. internal dividers are t hen set to generate the proper in ternal clocks. table 1 illustrates several standard audio sample rates and the required mclk and lrck frequencies. please note there is no re- quired phase relationship, but mclk, lrck and sclk must be synchronous. 3.2 mode select in hardware mode operation is determined by the mode select pins. the state of these pins are continually scanned for any changes. these pins require connection to supply or ground as outlined in figure 6. for m0, m1, m2 supply is vlc and for m3 and dsd_en supply is vls. tables 2 - 4 show the decode of these pins. in software mode the operational mode and data format are set in the fm and dif registers. ?parameter definitions? on page 41. speed mode (sample-rate range) sample rate (khz) mclk (mhz) software mode only mclk ratio 256x 384x 512x 768x 1024x* single-speed (4 to 50 khz) 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 mclk ratio 128x 192x 256x 384x 512x* double-speed (50 to 100 khz) 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 mclk ratio 64x 96x 128x 192x 256x* quad-speed (100 to 200 khz) 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 note: these modes are only available in software mode by setting the mclkdiv bit = 1. table 1. common clock frequencies
ds617pp1 21 cs4362a m1 (dif1) m0 (dif0) description format figure 00 left justified, up to 24-bit data 033 01 i 2 s, up to 24-bit data 134 10 right justified, 16-bit data 235 11 right justified, 24-bit data 336 table 2. digital interface format, stand-alone mode options m3 m2 (dem) description 00 single-speed without de-emphasis (4 to 50 khz sample rates) 01 single-speed with 44.1 khz de-emphasis; see figure 13 10 double-speed (50 to 100 khz sample rates) 11 quad-speed (100 to 200 khz sample rates) table 3. mode selection, stand-alone mode options dsd_en (lrck) m2 m1 m0 description 1 000 64x oversampled dsd data with a 4x mclk to dsd data rate 1 001 64x oversampled dsd data with a 6x mclk to dsd data rate 1 010 64x oversampled dsd data with a 8x mclk to dsd data rate 1 011 64x oversampled dsd data with a 12x mclk to dsd data rate 1 100 128x oversampled dsd data with a 2x mclk to dsd data rate 1 101 128x oversampled dsd data with a 3x mclk to dsd data rate 1 110 128x oversampled dsd data with a 4x mclk to dsd data rate 1 111 128x oversampled dsd data with a 6x mclk to dsd data rate table 4. direct stream digital (dsd), stand-alone mode options
22 ds617pp1 cs4362a 3.3 digital interface formats the serial port operates as a slave and supports the i2s, left-justified, and right-justified digital interface formats with varying bit depths from 16 to 24 as shown in figures 7-12. data is clocked into the dac on the rising edge. lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 7. format 0 - left -justified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb figure 8. format 1 - i 2 s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 9. format 2 - ri ght-justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 10. format 3 - ri ght-justified 24-bit data
ds617pp1 23 cs4362a 3.4 oversampling modes the cs4362a operates in one of three oversampling modes based on the input sample rate. mode selection is determined by the dsd_en, m3 and m2 pins in hardware mode or the fm bits in software mode. single- speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode supports input sample rates up to 200 khz and uses an oversampling ratio of 32x. 3.5 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the cs4362a incorpo- rates selectable interpolation filters for each mode of oper ation. a ?fast? and a ?slow? roll-off filter is available in each of single, double, and quad-speed modes. these filters have been designed to accommodate a variety of musical tastes and styles. the filt_sel bit is used to select which filter is used (see the ?param- eter definitions? on page 41 for more details). when in hardware mode, only the ?f ast? roll-off filter is available. filter specifications can be found in section 2, and filter response plots can be found in figures 19 to 42. 3.6 de-emphasis the cs4362a includes on-chip digital de-emphasis filt ers. the de-emphasis feature is included to accom- modate older audio recordi ngs that utilize pre-emphasis equalization as a means of noise reduction. figure 13 shows the de-emphasis curve. the frequency response of the de-emphasis curve will scale proportion- ally with changes in sample rate, fs if the input sample rate doe s not match the coefficient which has been selected. lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 11. format 4 - ri ght-justified 20-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 12. format 5 - ri ght-justified 18-bit data
24 ds617pp1 cs4362a in software mode the required de-emphasis filter coe fficients for 32 khz, 44.1 khz, or 48 khz are selected via the de-emphasis control bits. in hardware mode only the 44.1 khz coefficient is av ailable (enabled through the m2 pin). if the input sam- ple rate is not 44.1 khz and de-emphasis has been sele cted then the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual fs over 44,100. 3.7 atapi specification the cs4362a implements the channel mi xing functions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 7 on page 38 and figure 14 for additional informa- tion. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 13. de-emphasis curve ? a channel volume control aout ax aoutbx left chan nel audio d ata right chan nel audio d ata bchannel volume control mute mute sdinx figure 14. atapi block diagram (x = channel pair 1, 2, or 3)
ds617pp1 25 cs4362a 3.8 direct stream digital (dsd) mode in stand-alone mode, dsd operation is selected by holding dsd_en(lrck) high and applying the dsd data and clocks to the appropriate pins. the m[2:0] pins set the expected dsd rate and mclk ratio. in control-port mode the fm bits set the device into dsd mode (dsd_en pin is not required to be held high). the dif register then controls the expected dsd rate and mclk ratio. during dsd operation, the pcm related pins should either be tied low or remain active with clocks (except lrck in stand-alone mode). when the dsd related pins are not being used they should either be tied static low, or remain active with clocks (except m3 in stand-alone mode). 3.9 grounding and power supply arrangements as with any high resolution converter, the cs4362a requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. the typical connection diagram shows the recommended power arrangements, with va, vd, vlc, and vls connected to clean supplies. if the ground planes are split between digital ground and analog gr ound, the gnd pins of the cs4362a should be con- nected to the analog ground plane. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the dac. 3.9.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low value ceramic ca- pacitor being the closest. to further minimize impedance, these capacitors should be located on the same layer as the dac. if desired, all su pply pins with similar voltage ratings may be connected to the same sup- ply, but a decoupling capaci tor should still be placed on each supply pin. notes: all decoupling capacitors should be referenced to analog ground. the cdb4362a evaluation board demonstrates the optimum layout and power supply arrangements. 3.10 analog output and filtering the application note ?design notes fo r a 2-pole filter with differential input? discusses the second-order butterworth filter and differential to single-ended converter which was implemented on the cs4362a eval- uation board, cdb4362a, as seen in figure 16. th e cs4362a does not include phase or amplitude com- pensation for an external filter. th erefore, the dac system phase and am plitude response will be dependent on the external analog circuitry. the off-chip filter has been designed to attenuate the typical full-scale out- put level to below 2 vrms. figure 15 shows how the full-scale differential analog output level specification is derived.
26 ds617pp1 cs4362a 3.11 mute control the mute control pins go active during power-up initia lization, reset, muting, or if the mclk to lrck ratio is incorrect. these pins are intended to be used as control for external mute ci rcuits to prevent the clicks and pops that can occur in any single-ended single supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the cdb4362a data sheet for a suggested mute circuit. aout+ aout- full-scale output level= (aout+) - (aout-)= 6.7 vpp 3.85 v 2.5 v 1.15 v 3.85 v 2.5 v 1.15 v figure 15. full-scale output figure 16. recommended output filter
ds617pp1 27 cs4362a 3.12 recommended power-up sequence 3.12.1 hardware mode 1. hold rst low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1. in this state, the registers are reset to the defaul t settings, filt+ will remain low, and vq will be connected to va/2. if rst can not be held low long enough the sdinx pins should remain static low until all other clocks are stable, and if possible the rst should be toggled low again once the system is stable. 2. bring rst high. the device will remain in a low pow er state with filt+ lo w and will initiate the hardware power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). 3.12.2 software mode 1. hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1. in this state, the registers are reset to the default settings, filt+ will remain low, and vq will be connected to va/2. 2. bring rst high. the device will remain in a low power state with filt + low for 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad- speed mode). 3. in order to reduce the chances of clicks and pops, perform a write to the cp_en bit prior to the completion of approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad-speed mode). the desired register settings can be loaded while keeping the pdn bit set to 1. set the rmp_up and rmp_dn bits to 1, then set the format and mode control bits to the desired settings. if more than the stated number of lrck cycles passes before cpen bit is written then the chip will enter hardware mode and begin to operate with the m0-m3 as the mode settings. cpen bit may be written at anytime, even after the hardware sequence ha s begun. it is advised that if the cpen bit can not be set in time then the sdinx pins should remain static low (this way no audio data can be converted incorrectly by the hardware mode settings). 4. set the pdn bit to 0. this will initiate the power-up se quence, which lasts approximately 50 s. 3.13 recommended procedure for switching operational modes for systems where the absolute minimum in clicks and pops is required, it is recommended that the mute bits are set prior to changing significant dac function s (such as changing sample rates or clock sources). the mute bits may then be released after clocks have settled and the proper modes have been set. it is required to have the device held in reset if th e minimum high/low time spec s of mclk can not be met during clock source changes.
28 ds617pp1 cs4362a 3.14 control port interface the control port is used to load all the internal register settings in order to operate in software mode (see the ?parameter definitions? on page 41). the operatio n of the control port may be completely asynchronous with the audio sample rate. however, to avoid potentia l interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i 2 c or spi. 3.14.1 map auto increment the device has map (memory address po inter) auto increment capability e nabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i 2 c writes or reads and spi writes. if incr is set to 1, map will au to increment after each byte is wr itten, allowing bloc k reads or writes of successive registers. 3.14.2 i 2 c mode in the i 2 c mode, data is clocked into and out of the bi-direc tional serial control data line, sda, by the serial control port clock, scl (see figure 17 for the clock to data relationship). there is no cs pin. pin ad0 en- ables the user to alter the chip address (001100[ad0][r/w ]) and should be tied to vlc or gnd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 3.14.2.1 i 2 c write to write to the device, follow the procedure below while adhering to the control port switching specifi- cations in section 2. 1. initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of the ad0 pin, and t he eighth must be 0. the eighth bit of the address byte is the r/w bit. 2. wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3. wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4. if the incr bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i 2 c writes to other registers are de sired, it is necessary to ini- tiate a repeated start condition and follow the proced ure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus.
ds617pp1 29 cs4362a 3.14.2.2 i 2 c read to read from the device, follow the procedure below while adhering to the cont rol port switching spec- ifications. 1. initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of t he ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2. after transmitting an acknowledg e (ack), the device will then transmit the cont ents of the register pointed to by the map. th e map register will contain the address of the last register written to the map, or the default address (see section 3.14.1) if an i 2 c read is the first operation performed on the device. 3. once the device has transmitted the contents of the register pointed to by the map, issue an ack. 4. if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. continue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i 2 c reads from other registers ar e desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from steps 1 and 2 from the i 2 c write instructions followed by step 1 of the i 2 c read section. if no further reads from other registers are desired, initiate a stop condition to the bus. sda scl 001100 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 17. control port timing, i 2 c mode
30 ds617pp1 cs4362a 3.14.3 spi ? mode in spi mode, data is clocked into t he serial control data line, cdin, by the serial control port clock, cclk (see figure 18 for the clock to data re lationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 3.14.3.1 spi write to write to the device, follow the procedure below while adhering to the control port switching specifi- cations in section 2. 1. bring cs low. 2. the address byte on the cdin pin must then be 00110000. 3. write to the memory address pointer, map. this byte points to the register to be written. 4. write the desired data to the register pointed to by the map. 5. if the incr bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6. if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are desired, bring cs high. 3.15 memory address po inter (map) map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0011000 figure 18. control port timing, spi mode 3.15.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 3.15.2 map4-0 (memory address pointer) default = ?00000? 76543210 incr reserved reserved map4 map3 map2 map1 map0 00000000
ds617pp1 31 cs4362a 4. register qu ick reference addr function 7 6 5 4 3 2 1 0 01h mode control 1 cpen freeze mclkdiv reserved dac3_dis dac2_dis dac1_dis pdn default 00 0 00001 02h mode control 2 reserved dif2 dif1 dif0 reserved reserved reserved reserved default 00000000 03h mode control 3 szc1 szc0 snglvol rmp_up mutec+/- amute mutec1 mutec0 default 10000100 04h filter control reserved reserved reserved filt_sel reserved dem1 dem0 rmp_dn default 00000000 05h invert control reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 00000000 06h mixing control pair 1 (aoutx1) p1_a=b p1atapi4 p1atapi3 p1atapi2 p1atapi1 p1atapi0 fm1 fm0 default 00100100 07h vol. control a1 a1_mute a1_vol6 a1_vol 5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 00000000 08h vol. control b1 b1_mute b1_vol6 b1_vol 5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 00000000 09h mixing control pair 2 (aoutx2) p2_a=b p2atapi4 p2atapi3 p2atapi2 p2atapi1 p2atapi0 reserved reserved default 00100100 0ah vol. control a2 a2_mute a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 00000000 0bh vol. control b2 b2_mute b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 00000000 0ch mixing control pair 3 (aoutx3) p3_a=b p3atapi4 p3atapi3 p3atapi2 p3atapi1 p3atapi0 reserved reserved default 00100100 0dh vol. control a3 a3_mute a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 00000000 0eh vol. control b3 b3_mute b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 00000000 12h chip revision part4 part3 part2 part1 part0 rev rev rev default 01010 x x x
32 ds617pp1 cs4362a 5. register description note: all registers are read/write in i 2 c mode and write only in spi, unless otherwise noted. 5.1 mode control 1 (address 01h) 5.1.1 control port enable (cpen) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing the device to power- up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. th is will allow the operation of the device to be co ntrolled by the registers and the pin definitions will c onform to control port mo de. to accomplish a clean power-up, the user should write this bit within 10 ms following the release of reset. 5.1.2 freeze controls (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to th e registers without the changes taking effect until the freeze is disabled. to make multip le changes in the control port registers take effect simultaneously, en- able the freeze bit, make all register changes, then disable the freeze bit. 5.1.3 master clock divi de enable (mclkdiv) default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the exte rnally applied mclk signal by 2 prior to all other internal circuitry. 5.1.4 dac pair di sable (dacx_dis) default = 0 0 - enabled 1 - disabled function: when enabled the respective dac channel pair x (aoutax and aoutbx) will remain in a reset state. it is advised that changes to these bits be made while the power do wn bit is enabled to eliminate the possibility of audible artifacts. 76543210 cpen freeze mclkdiv reserved dac3_dis dac2_dis dac1_dis pdn 00000001
ds617pp1 33 cs4362a 5.1.5 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when this functi on is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be dis- abled before normal operation in control port mode can occur. 5.2 mode control 2 (address 02h) 5.2.1 digital interface format (dif) default = 000 - format 0 (left justified, up to 24-bit data) function: these bits select the interface format for the serial au dio input. the functional mode bits determine wheth- er pcm or dsd mode is selected. pcm mode: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 7-12. dsd mode: the relationship between the oversampling rati o of the dsd audio data and the required mas- ter clock to dsd data rate is defined by the digital interface format pins. 76543210 reserved dif2 dif1 dif0 reserv ed reserved reserved reserved 00000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 07 001 i 2 s, up to 24-bit data 18 010 right justified, 16-bit data 29 011 right justified, 24-bit data 310 100 right justified, 20-bit data 411 101 right justified, 18-bit data 512 110 reserved - 111 reserved - table 5. digital interface formats - pcm mode dif2 dif1 difo description 0 0 0 64x oversampled dsd data wit h a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data wit h a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data wit h a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 6. digital interface formats - dsd mode
34 ds617pp1 cs4362a 5.2.2 mode control 3 (address 03h) 5.2.3 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross zero cross enable dictates that signal level changes , either by attenuation c hanges or muting, will occur on a signal zero crossing to minimi ze audible artifacts. t he requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross functi on is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and atte nuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current le vel to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a sign al zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing . the zero cross function is independently monitored and implemented for each channel. 5.2.4 single volume control (snglvol) default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independently controlled by their respec tive volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel volume con- trol byte, and the other volume control bytes are ignored when this function is enabled. 76543210 szc1 szc0 snglvol rmp_up mutec+/- amute mutec1 mutec0 10000100
ds617pp1 35 cs4362a 5.2.5 soft volume ramp-u p after error (rmp_up) default = 0 0 - disabled 1 - enabled function: an un-mute will be performed after a lrck/mclk ratio change or error, and after changing the functional mode. when this feature is enabled, this un-mute is af fected, similarly to attenuation changes, by the soft and zero cross bits in the mode control 3 register. when disabled, an immediate un-mute is performed in these instances. notes: for best results, it is recommended that this fe ature be used in conjunction with the rmp_dn bit. 5.2.6 mutec polarity (mutec+/-) default = 0 0 - active high 1 - active low function: the active polarity of the mutec pin( s) is determined by this register. when set to 0 (default) the mutec pins are high when active. when set to 1 the mutec pin(s) are low when active. notes: when the on board mute circuitry is designed for active low, the mu tec outputs will be high (un-muted) for the period of time during reset and before this bit is enabled to 1. 5.2.7 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter outp ut will mute following the reception of 8192 consecut ive audio samples of static 0 or -1. a single sample of non-static data will release the mute. de tection and muting is done independently for each channe l. the quiescent voltage on the output will be retain ed and the mute control pin will go active during the mute period. the muting fu nction is affected, similar to volume control changes, by the soft and zero cross bits in the mode control 3 register. 5.2.8 mute pin control (mutec1, mutec0) default = 00 00 - six mute control signals 01, 10 - one mute control signal 11 - three mute control signals function: selects how the internal mute control signals are r outed to the mutec1 through mutec6 pins. when set to ?00?, there is one mute control signal for each channel: aout1a on mutec1, aout1b on mutec2, etc. when set to ?01? or ?10?, there is a single mute control signal on the mutec1 pin. when set to ?11?, there are three mute control signals, one for each stereo pair: aout1a and aout1b on mutec1, aout2a and aout2b on mutec2, and aout3a and aout3b on mutec3.
36 ds617pp1 cs4362a 5.3 filter control (address 04h) 5.3.1 interpolation filt er select (filt_sel) default = 0 0 - fast roll-off 1 - slow roll-off function: this function allows the user to select whether the inte rpolation filter has a fast or slow roll off. for filter characteristics please see section 2. 5.3.2 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 khz sample rates. (see figure 13) de-emphasis is only available in single speed mode. 5.3.3 soft ramp-down before fi lter mode change (rmp_dn) default = 0 0 - disabled 1 - enabled function: if either the filt_sel or dem bits are changed the dac will stop conversi on for a period of time to change filter values. this bit selects how the data is effected prior to and after the change of the filter values. when this bit is enabled the dac will ramp down the volume prior to a filter mode change and ra mp from mute to the original volume value after a filter mode change ac cording to the settings of the soft and zero cross bits in the mode control 3 register. when disabl ed, an immediate mute and unmute is performed. loss of clocks or a change in the fm bits will always cause an immediat e mute; unmute in these conditions is affected by the rmp_up bit. notes: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 76543210 reserved reserved reserved filt _sel reserved dem1 dem0 rmp_dn 00000000
ds617pp1 37 cs4362a 5.4 invert control (address 05h) 5.4.1 invert signal polarity (inv_xx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 5.5 mixing control pair 1 (cha nnels a1 & b1)(address 06h) mixing control pair 2 (channe ls a2 & b2)(address 09h) mixing control pair 3 (channe ls a3 & b3)(address 0ch) 5.5.1 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are independ ently controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both aoutax and aoutbx are determined by the a channel attenuation and volume control bytes (per a-b pair), and the b channel bytes are ig- nored when this function is enabled. 5.5.2 atapi channel mixing and muting (atapi) default = 01001 - aoutax =al, aoutbx=br (stereo) function: the cs4362a implements the channel mixi ng functions of the atapi cd- rom specification. the atapi functions are applied per a-b pair. refer to table 7 and figure 14 for additional information. 76543210 reserved reserved inv_b3 inv_ a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 px_a=b pxatapi4 pxatapi3 pxatapi2 pxatapi1 pxatapi0 pxfm1 pxfm0 00100100
38 ds617pp1 cs4362a 5.5.3 functional mode (fm) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - direct stream digital mode function: selects the required range of input sample rates or dsd mode. all dac pairs are required to be set to the same functional mode setting before a speed mode change is accepted. when dsd mode is selected for any channel pair then all pa irs will switch to dsd mode. atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 01111 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 7. atapi decode
ds617pp1 39 cs4362a 5.6 volume control (addresses 07h , 08h, 0ah, 0bh, 0dh, 0eh) note: these six registers provide individual volume and mute control for each of the six channels. the values for ?xx? in the bit fields above are as follows: register address 07h - xx = a1 register address 08h - xx = b1 register address 0ah - xx = a2 register address 0bh - xx = b2 register address 0dh - xx = a3 register address 0eh - xx = b3 5.6.1 mute (mute) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter ou tput will mute when enabled. the qu iescent voltage on the output will be retained. the muting function is affected, similarly to attenuation changes, by the soft and zero cross bits. the mute pins will go active during the mu te period according to the mutec bits. 5.6.2 volume control (xx_vol) default = 0 (no attenuation) function: the digital volume control registers allow independent control of the signal levels in 1 db increments from 0 to -127 db. volume settings are decoded as shown in table 8. the volume changes are implemented as dictated by the soft and zero cross bits. all volume settings less than -127 db are equivalent to enabling the mute bit. 76543210 xx_mute xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 0 0 0 0 0 0 0 0 0 db 0 0 1 0 1 0 0 20 -20 db 0 1 0 1 0 0 0 40 -40 db 0 1 1 1 1 0 0 60 -60 db 1 0 1 1 0 1 0 90 -90 db table 8. example digital volume settings
40 ds617pp1 cs4362a 5.7 chip revision (address 12h) 5.7.1 part number id (part) [read only] 01010 - cs4362a 000 - revision a function: this read-only register can be used to identify the model and revision number of the device. 76543210 part4 part3 part2 part1 part0 reserved reserved reserved 01010000
ds617pp1 41 cs4362a 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-n oise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measure- ment to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement te chnique has been accepted by the audio engineer- ing society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 7. references note: "how to achieve optimum performance from delta-si gma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. note: cdb4362a datasheet note: ?design notes for a 2-pole f ilter with differential input? by steven gr een. cirrus logic application note an48 note: ?the i 2 c-bus specification: version 2.0? ph ilips semiconductors, december 1998. http://www.semiconduc tors.philips.com 8. ordering information product description package pb-free grade temp range container order # cs4362a 114 db, 192 khz 6- channel d/a converter 48-pin lqfp yes commercial -10 to +70 c tray CS4362A-CQZ tape & reel CS4362A-CQZr automotive -40 to +105 c tray cs4362a-eqz tape & reel cs4362a-eqzr cdb4362a cs4362a evaluation board - - - - cdb4362a
42 ds617pp1 cs4362a 9. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds617pp1 43 cs4362a 10.appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 19. single-speed (fast) stopband rejectio n figure 20. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 21. single-speed (fast) transition band (detail) figure 22. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 23. single-speed (slow) stopband rejection figure 24. sing le-speed (slow) transition band
44 ds617pp1 cs4362a 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 25. single-speed (slow) transition band (d etail) figure 26. single-s peed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 27. double-speed (fast) stopband rejectio n figure 28. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 29. double-speed (fast) transition band (detail) figure 30. double-speed (fast) passband ripple
ds617pp1 45 cs4362a 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 31. double-speed (slow) stopband rejection figure 32. doub le-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 33. double-speed (slow) transition band (d etail) figure 34. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 35. quad-speed (fast) stopband rejection figure 36. quad-speed (fast) transition band
46 ds617pp1 cs4362a 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 37. quad-speed (fast) transition band (detail) figure 38. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 39. quad-speed (slow) stopband rejectio n figure 40. quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 41. quad-speed (slow) transition band (det ail) figure 42. quad-speed (slow) passband ripple
ds617pp1 47 cs4362a table 9. revision history release date changes a1 nov 2004 initial release pp1 apr 2005 updated output impedance spec on page 10 improved interchannel isolation spec on page 10 updated legal text re-formatted order ing information contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the informat ion is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version o f relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation of liability. no responsibility is assu med by cirrus for the use of this infor- mation, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage ("critical applications"). ci rrus products are not designed, authorized or warranted for use in aircraft systems, milita ry applications, product s surgically implanted into the body, automotive safety or security devices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, includ- ing the implied warranties of merchantability and fitness fo r particular purpose, with regard to any cirrus product that is used in such a manner. if the custo mer or customer's custo mer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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